8-Bit
SAA-XC886CLM
8-Bit Single Chip Microcontroller
Data Sheet
V1.1 2010-08
M icr o con t ro l le r s
Edition 2010-08
Published by
Infineon Technologies AG
81726 Munich, Germany
©
2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
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Warnings
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question, please contact the nearest Infineon Technologies Office.
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8-Bit
SAA-XC886CLM
8-Bit Single Chip Microcontroller
Data Sheet
V1.1 2010-08
M icr o con t ro l le r s
SAA-XC886CLM
SAA-XC886 Data Sheet
Revision History: V1.1 2010-08
Previous Versions: V1.0 2009-09
Page
126
126
126
Subjects (major changes since last revision)
New parameter on weighted average temperature is added.
Maximum value of parameter
V
CDM
is increased from 500 V to 750 V.
Parameter
V
CDM
is no longer differentiated between
V
DDC
and all other pins.
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Data Sheet
V1.1, 2010-08
SAA-XC886CLM
Table of Contents
Table of Contents
1
2
2.1
2.2
2.3
2.4
3
3.1
3.2
3.2.1
3.2.1.1
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.2.3.1
3.2.4
3.2.4.1
3.2.4.2
3.2.4.3
3.2.4.4
3.2.4.5
3.2.4.6
3.2.4.7
3.2.4.8
3.2.4.9
3.2.4.10
3.2.4.11
3.2.4.12
3.2.4.13
3.2.4.14
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
Summary of Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Device Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAA-XC886 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Read Access of P-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Programming Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-1
4
4
5
6
7
16
16
17
18
18
20
20
22
26
27
28
28
29
30
31
33
34
36
40
40
41
45
46
46
47
49
50
51
52
53
53
59
61
62
Data Sheet
V1.1, 2010-08
RF/无线
